A 1.8 V 10-bit 80 MS/s low power track-and-hold circuit in a 0.18µm CMOS process

A 10-bit low power track-and-hold (T&H) circuit aimed for the front-end of a pipelined analog-to-digital (A/D) converter has been designed. The T&H is sampling at 80MS/s, has a 30MHz analog bandwidth and was designed in a 0.18μm CMOS process with a supply voltage of 1.8 Volt. A switched capacitor topology applying correlated double sampling is used for the T&H circuit and the amplifier is a folded cascode OTA with gain boosting. This paper describes the design of the complete T&H, including the derivation of the specifications as well as a straightforward approach for designing the transmission gate switches.